An integrated circuit such as a system-on-a-chip (SoC) often includes sub-systems such as receivers and transmitters that are clocked by corresponding clock signals. To keep the various sub-systems synchronized, it is conventional for an SoC to include a reference clock transmitter that provides a reference clock to a plurality of PLLs. The use of fractional-N PLLs provides greater flexibility with regard to the clocking frequency. In contrast, the clock frequency from an integer-N PLL has an integer relationship to the reference clock. But a fractional-N PLL untethers the sub-system clocking from such an integer relationship so that the sub-system clock frequencies can have a non-integer relationship to the reference clock. Such a non-integer relationship is particularly useful in modern telecommunication standards such as Long Term Evolution (LTE) or 5G in which a cellular handset is assigned a certain frequency band across an operating bandwidth. The frequency flexibility of a fractional-N PLL enables the handset to operate in its assigned frequency band. To provide additional frequency tuning or flexibility, the output signal from a fractional-N PLL may be divided in a post divider. For example, an RF receiver or transmitter may form a local oscillator (LO) signal using such a post divider on the PLL output signal from a fractional-N PLL.
But frequency agility is not the only concern in fractional-N PLL design. In addition, SoC components must also have low power consumption to preserve battery life. It is thus conventional for a subsystem's PLL to be shut down or enter a sleep mode during idle periods. During sleep mode operation, the post divider is shut down and then powered back up when the PLL resumes normal operation. The LO output signal from the post divider will then have an unknown phase relationship with the reference clock frequency. For example, if the post divider divides the PLL output signal by two, the LO output signal may have either a 0 degree or 180 degree phase relationship to the reference clock frequency. Such an arbitrary phase relationship between the LO output signal and the reference clock signal upon resumption of normal operation degrades system performance. It is thus desirable to keep the post divider phase constant, both before and after sleep mode operation.
Despite the need to maintain such constant phase, current post divider phase continuity schemes are problematic. An example phase continuity architecture for a fractional-N PLL 100 is shown in FIG. 1. Fractional-N PLL 100 includes an analog portion 105 for generating a PLL output signal 170. To keep PLL output signal 170 phase aligned with a reference clock signal Fref, PLL output signal 170 is divided in a feedback divider 130 to form a divided clock signal (Fdiv) 165 that is compared with the reference clock signal (Fref) in a phase detector (PFD) 110. Depending upon whether the divided clock signal is leading or lagging the reference clock signal, phase detector 110 asserts either an up signal (Up) or a down signal (Dn). A charge pump 115 charges a charge pump output signal (Icp) if the up signal is asserted or discharges the charge pump output signal if the down signal is asserted. After filtering in a loop filter 120, the charge pump output signal becomes a tuning control voltage Vtune that controls the frequency of a voltage-controlled oscillator VCO 125. Should feedback divider 130 divide by a constant integer N, analog portion 105 forms a conventional integer-N PLL. However, fractional-N PLL 100 also includes a digital portion 135 that toggles or dithers the integer N used by fractional divider 130 to effect the desired integer plus some fraction relationship between the frequency of the reference clock signal and the clocking signal frequency for PLL output signal 170.
To perform the incrementing or dithering of the integer N used by feedback divider 130 to divide PLL output signal 170, digital portion 135 includes a phase accumulator or phase control circuit 140. As known in the fractional-N PLL arts, the fractional portion of the relationship between the reference clock signal frequency and the output clock signal frequency may be represented by a ratio (K/M), where K and M are positive integers. This ratio may also be represented by a fraction F. M is the modulus for the counting in phase control circuit 145 whereas K in the increment successively added to the phase accumulator count. Phase control circuit 140 thus receives the factor N.F, to identify the integer divider N and the fractional portion F. In one embodiment, the feedback divider 130 may be configured to divide by N+1 instead of N every time the modulo-N counting in phase control circuit 145 overflows. But such fractional-N PLL operation is then prone to developing undesirable spurs in the frequency spectrum for PLL output signal 170. To reduce such spurs, digital portion 135 may also include a delta-sigma modulator (DSM) 150 that further dithers the incrementing of the divisor N by feedback divisor 130.
A local oscillator portion 175 post divides PLL output signal 170 in a post divider 180 to form a local oscillator (LO output signal. For example, post divider 180 may divide output clock by 2, or by 3, or by 4, and so on to form the LO output signal. But such a post division following a sleep mode of operation may change the phase relationship between the LO output signal and the reference clock as compared to the phase relationship that existed prior to the sleep mode. For example, with regard to a post division by two, one sub-system clock signal may be out of phase with another sub-system clock signal by 0 degrees or by 180 degrees phase such that the phase relationship becomes uncertain. To maintain a known phase relationship, the LO output signal is sampled by a register 185 as clocked by divided clock signal 165 from feedback divider 130. A digital LO phase corrector circuit 155 in digital portion 135 receives the sampled output from register 185 to sample the phase of the LO output signal. Depending upon the sampled phase, digital LO phase corrector circuit 155 adjusts the dithering of the feedback division by adding to the output of DSM 150 in an adder 160. Feedback divider 130 then adjusts its division responsive to a summed output signal from adder 160.
But note that LO portion 175 may be relatively remote from analog portion 105 such that PLL output signal 170 must be buffered for suitable propagation to LO portion 175. Divided clock signal 165 must then be similarly buffered across this propagation distance. The matching of the transmission channels for the PLL output signal 170 and divided clock signal 165 is quite difficult and cumbersome, particularly with regard to temperature and voltage drifts. Maintaining phase continuity for LO portion 175 is thus quite problematic.
Accordingly, there is a need in the art for improved phase continuity schemes for the post division of a PLL output signal from a fractional-N PLL.